I. Non-Volatile Memory Devices
Non-volatile memory devices, and particularly so-called "flash" memory devices have become increasingly popular in data storage applications. The term EPROM is an acronym for Erasable Programmable Read Only Memory, while EEPROM refers to Electrically Erasable Programmable Read Only Memory. The term "flash" in conjunction with electrical erasable programmable read only memory or "Flash EEPROMS", generally refers to EEPROM memory cells which are programmed by hot electron injection and erased by Fowler-Nordheim tunneling. The operation and structure of one type of such devices, namely NOR devices, is discussed in U.S. Pat. No. 4,698,787, issued Oct. 6, 1987, to Mukherjee et al., and Samachisa et al., "A 128K Flash EEPROM Using Double Polysilicon Technology," IEEE Journal of Solid State Circuits, 22(5):676-683 (October 1987), both references herein incorporated fully by reference. The operation and structure of another type of such devices, namely NAND devices, is discussed in Suh et al., A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme, IEEE Journal of Solid-State Circuits 30(11):1149-1155 (November 1995), herein incorporated fully by reference.
Generally, an array of flash EPROM or EEPROM memory cells can be formed on a semiconductor substrate in a series of rows and columns, accessed by conductors referred to as word lines and bit lines, respectively. FIG. 1 depicts the relationship between different regions of a semiconductor chip 10. Memory cells can be arranged typically in a common region, referred to as the "core" area 121 of chip 10. Other devices necessary for the operation of the device, such as the peripheral transistors and amplifiers, can be located in the "periphery" region 120 of chip 10. In the core region, all memory cells or other devices can have essentially the same dimensions, allowing simultaneous fabrication of the cells in the core region using common processing steps.
Each memory cell is formed in a semiconductor substrate, by way of example only, by the diffusion into what will become an n+ source region and an n+ drain region, of an n type dopant, such as by way of example only, phosphorous or arsenic. A channel region can be positioned between the drain and source regions. The channel region between the source and drain regions is the location where the memory cell "gate stack" or "gate" is to be located. The channel region can be typically doped with a p-type dopant, by way of example only, boron. This doping step is termed an "implantation step." Typically, prior to the manufacture of the gate stack, a layer of tunnel oxide can be formed on the silicon substrate of the channel region after the implantation step. By way of example only, such tunnel oxide can be manufactured by reacting the silicon substrate at elevated temperatures in the presence of O.sub.2 and N.sub.2 O or NO. This process, termed "nitridation" enhances interface bonding states between silicon dioxide and the silicon substrate, thereby improving the reliability of tunnel oxide. After the creation of the tunnel oxide layer, typically a layer of conductive material such as polysilicon can be deposited on the top of the tunnel oxide layer, resulting in the formation of a "floating gate." Subsequently, a dielectric layer can be formed over the polysilicon layer, and another layer of polysilicon or other conductive material can be deposited over the dielectric layer, forming a "control gate." The control gate is connected to a source of electrical charge, and the entire structure consisting of the sandwich of polysilicon layers separated by a dielectric layer is termed the "control gate stack."
The application of voltage to the control gate can induce a charge in the floating gate. If there is a net positive charge in the floating gate, there can be an induced change in the channel region between the source and drain regions, and electrons can flow from the source region to the drain regions of the device, and the device is considered to be "on." The creation of charge in the floating gate is termed "programming" of the floating gate of the memory cell.
Programming and erasing of these structures is achieved by creating potential differences between the gate and the channel or drain lines. The thin tunnel oxide region coupled with the high voltage difference between gate and drain can permit a phenomenon called "Fowler-Nordheim tunneling" to take place. Programming the floating gate involves placing electrons on the gate. To program an EPROM or an EEPROM cell, a hot injection mechanism can be typically used.
Typically, for NAND type architecture, all cells are in series. In the read mode, selected word lines have 0 V placed on the control gate, and a voltage of about 4.5 V is applied to unselected word lines. The magnitude of the current resulting from application of the read voltage, the "read current" can be used to determine whether the flash EPROM or EEPROM cell is programmed or not. If the application of the read voltage results in current flow, then the memory cell is in the un-programmed state. However, if application of the read voltage does not result in a read current, the memory cell is in the programmed state.
For most memory storage applications, it is desirable for the floating gates to retain the charge applied to them for long periods of time. However, with conventional non-volatile memory devices, the erase charge in the memory cell can be lost. With the loss of the erase charge, the floating gate can become unintentionally programmed, which can lead to product failure. Nitridation of tunnel oxide layers can reduce unintentional programming or de-programming by reducing either unintentional charge loss or charge gain. However, the current methods for carrying out tunnel oxide nitridation can have the unintended effect of causing electrical reliability problems in the devices fabricated on the periphery regions of the semiconductor wafer. These problems can arise from contamination of silicon regions where gate oxide layers are to be formed by nitrogen introduced during nitridation.
II. Manufacture of Non-Volatile Memory Devices
The manufacture of semiconductor memory devices begins with a wafer of silicon on which all of the devices are to be manufactured. The first step involves the creation of isolation regions which serve to electrically isolate the active regions from each other, followed by manufacture of active regions, containing sources, drains, and gate stacks. Electrical isolation may be via the formation of Shallow Trench Isolation ("STI") wherein grooves are etched in the silicon wafer and are filled with insulating materials termed "dielectric" materials. Alternatively, the Local Oxidation Of Silicon ("LOCOS") process can be used, wherein areas of insulating materials are formed on the surface of the wafer to provide electrical isolation of active regions. Therefore, to minimize the size of semiconductor devices, one aim of manufacturers is to make the isolation regions narrow. Narrower isolation regions can permit the manufacture of semiconductor integrated circuits having higher device densities, which can lead to increased performance and decreased manufacturing cost
A. Local Oxidation of Silicon (LOCOS)
In the LOCOS process, the isolation regions on the wafer can be made by oxidation product of silicon to produce silicon dioxide. When sufficiently thick, silicon dioxide can be an effective insulator, preventing unwanted electrical interaction between nearby devices. To manufacture isolation regions using the LOCOS process, the wafer surface can be first covered with a layer of nitride, such as silicon nitride (Si.sub.3 N.sub.4). The silicon nitride can inhibit the diffusion of oxygen into the underlying silicon wafer, thereby preventing the undesired oxidation of the silicon layer where active devices are to be manufacture. In those areas of the wafer where isolation regions are to be created, the silicon nitride layer can be selectively removed, or "etched," exposing the underlaying silicon surface. Subsequently, the exposed areas of silicon can be oxidized, typically by heating the wafer in a furnace containing an oxidizing agent such as oxygen or ozone. When masked with the nitride layer, exposure of the wafer to oxidizing conditions ideally can result in formation of SiO.sub.2 only on the surfaces of those portions of the wafer which are not covered by the nitride layer. Thus, local areas of oxide, termed "field oxide" can be formed, and can become the insulators which isolate semiconductor devices from one another on the wafer. SiO.sub.2 is less dense than silicon, so the formation of field oxide regions results in the appearance of a thickening of the wafer surface at those locations.
However, when oxidation is carried out as described, heating the wafer can result in thermal expansion of both the silicon and nitride layers. Because nitride and silicon have different coefficients of thermal expansion, the heating can result in differential expansion of the two materials. This can lead to de-lamination of the nitride layer, causing undesired oxidation of the silicon under the edges of the nitride layer, and can result in the spreading of the field oxide region under the nitride layer, forming what are termed "birds beaks." The formation of birds beaks effectively can decrease the area available for active regions of the semiconductor devices, and can defeat one of the purposes of using the LOCOS process, namely the increase in device density on a semiconductor wafer. As further oxidation occurs, the delamination also can increase, and thus, the sizes of the birds beaks can increase, further diminishing the size for formation of active regions on the wafer.
One way of diminishing the size of birds beaks is to apply a thin layer of oxide ("pad oxide") over the silicon wafer before deposition of the nitride layer. Pad oxide has a coefficient of thermal expansion similar to that of the nitride masking material, so subsequent exposure of the wafer to high temperatures does not necessarily delaminate the nitride layer as much as is the case with nitride on unoxidized silicon.
B. Formation of Active Regions and ONO Layers
After the formation of field oxide regions, active regions are manufactured. First, the nitride layer is etched away to expose the underlying silicon dioxide. Typically, the wafer is then exposed to a nitridation step, wherein a relatively thin layer of tunnel oxide (SiO.sub.2) about 90 .ANG. thick is nitrided by exposure to N.sub.2 O or NO and annealed. The resulting nitrided tunnel oxide layer is about 95 .ANG. in thickness. The resulting structure is shown in FIG. 2. FIG. 2 shows a typical section of a semiconductor wafer 200 having a periphery region 120 and a core region 121 made using the above steps. Silicon substrate 104 has regions of field oxide 108 deposited thereon, with areas of nitrided tunnel oxide 112 therebetween. This function of this thin layer of tunnel oxide is to promote the movement of charge from the source, drain, or silicon substrate to the floating gate.
After the nitridation step, a layer of a polysilicon is deposited over the entire wafer. The polysilicon layer can be subsequently etched to form floating gate regions ("poly 1"), which will function to store charge in the device after programming. After etching of the polysilicon layer, sequential deposition and etching of layers of SiO.sub.2, nitride, and SiO.sub.2 (the "ONO" step) provide a total thickness of the ONO layer of about 150 .ANG..
C. Formation of Periphery Devices
After ONO deposition, devices in the periphery of the semiconductor chip are then manufactured. The entire wafer can then be covered with photoresist. An ONO mask is placed over the core region, leaving the periphery uncovered. Exposure of the photoresist to electromagnetic radiation, followed by developing the photoresist layer reveals the underlying periphery circuit region. Then the ONO layer and poly 1 layer are etched in the periphery, followed by HF treatment to remove the oxide layer in areas where active devices are to be manufactured. Then the layer of photoresist can be removed by a cleaning step. The silicon layer is then carefully oxidized to grow a region of "gate oxide" about 150 .ANG. in thickness for the subsequent manufacture of active periphery devices.
After the gate oxide is formed on the silicon at the periphery region, a layer of polysilicon ("poly 2") can be deposited over the entire wafer. In the core region, this poly 2 layer can become the control gate of the memory cell. In the periphery, the poly 2 layer can be deposited directly over the gate oxide regions, and subsequently, as desired for the particular device to be manufactured, layers of silicide, typically tungsten silicide, and silicon oxynitride can be deposited and etched to form the devices in the periphery region of the chip.
Subsequent processing steps can include formation of contacts, contact etching, metal deposition, metal etching, passivation layer deposition, and pad formation. These steps are known in the art and are not described herein further. The resulting periphery devices can then be connected to the core devices to complete the manufacture of the integrated circuit.
Problems with the above described methods of manufacturing gate oxide layers in the periphery in this fashion can result from the nitridation step of the core region. Nitridation can result in the contamination by nitrogen atoms of the silicon substrate region in the periphery regions where the gate oxide and active regions are to be manufactured. The presence of nitrogen in the silicon layer can cause the gate oxide layer to grow more slowly than in areas where there is no nitrogen contamination. The localization and degree of nitrogen contamination can be unpredictable, and as a result, gate oxide layers in the periphery can be formed having uneven thickness and density. The un-evenness can result in non-uniformity of electrical properties of the gate oxide. In areas with little or no nitrogen contamination, the gate oxide layer can be about 150 .ANG. in thickness, which provides a breakdown voltage of about 15 V. However, in areas which are contaminated by nitrogen, the thickness of the gate oxide can be as low as about 50 .ANG., which provides a breakdown voltage of about 10 V or less, and can even be as low as 2-3 V. Thus, different parts of the gate oxide region can have different breakdown voltages, and because the overall breakdown voltage of a gate can be determined by the lowest breakdown value of the oxide present in that gate, the gate as a whole can exhibit a reduced breakdown voltage, which can lead to failure of devices in the periphery region. Therefore, the conventional methods are incapable of producing reproducible gate oxide layers in peripheral regions having high breakdown voltages, while permitting the nitridation of tunnel oxide, which is desirable for the manufacture of non-volatile memory cells.
Therefore, one object of this invention is the development of methods to manufacture gate oxide layers with improved uniformity and higher, more predictable electrical breakdown voltage.
Another object of this invention is the development of methods for manufacturing periphery gate oxide layers having reduced nitrogen contents.
Another object of this invention is the manufacture of semiconductor devices having improved gate oxide uniformity and higher, more predictable electrical breakdown voltage.
Yet another object of this invention is the manufacture of semiconductor devices having gate oxide regions with reduced nitrogen contents.